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| IS61C64B 8K x 8 HIGH-SPEED CMOS STATIC RAM FEATURES * High-speed access time: 10, 12, and 15 ns * Automatic power-down when chip is deselected * CMOS low power operation -- 450 mW (typical) operating -- 250 W (typical) standby * TTL compatible interface levels * Single 5V power supply * Fully static operation: no clock or refresh required * Three state outputs * One Chip Enables (CE) for increased speed ISSI July 2002 (R) DESCRIPTION The ISSI IS61C64B is a very high-speed, low power, 8192-word by 8-bit static RAM. It is fabricated using ISSI's highperformance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 10 ns with low power consumption. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 250 W (typical) with CMOS input levels. Easy memory expansion is provided by using one Chip Enable input, CE. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS61C64B is packaged in the JEDEC standard 28-pin, 300-mil SOJ, and TSOP. FUNCTIONAL BLOCK DIAGRAM A0-A12 DECODER 256 X 256 MEMORY ARRAY VCC GND I/O DATA CIRCUIT I/O0-I/O7 COLUMN I/O CE OE WE CONTROL CIRCUIT Copyright (c) 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. D 07/01/02 IS61C64B TRUTH TABLE Mode Not Selected (Power-down) Output Disabled Read Write WE X X H H L CE H X L L L OE X X H L X I/O Operation High-Z High-Z High-Z DOUT DIN Vcc Current ISB1, ISB2 ISB1, ISB2 ICC ICC ICC ISSI (R) PIN CONFIGURATION 28-Pin SOJ PIN CONFIGURATION 28-Pin TSOP (Type 1) * A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE * A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 OE A11 A9 A8 WE VCC A12 A7 A6 A5 A4 A3 * * 22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 19 18 17 16 15 14 13 12 11 10 9 8 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 PIN DESCRIPTIONS A0-A12 CE OE WE I/O0-I/O7 * Vcc GND Address Inputs Chip Enable 1 Input Output Enable Input Write Enable Input Input/Output Must be tied to either Vcc or GND Power Ground Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. D 07/01/02 IS61C64B ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TBIAS TSTG PT IOUT Parameter Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current (LOW) Value -0.5 to +7.0 -10 to +85 -65 to +150 1.0 20 Unit V C C W mA ISSI (R) 1 2 3 4 Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE Range Commercial Ambient Temperature 0C to +70C Speed 10 ns 12 ns 15 ns VCC 5V 5% 5V 10% 5V 10% 5 6 Min. 2.4 -- 2.2 -0.5 Max. -- 0.4 VCC + 0.5 0.8 2 2 Unit V V V V A A DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage GND - VIN - VCC GND - VOUT - VCC, Outputs Disabled Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 7 8 9 10 11 12 -2 -2 Notes: 1. VIL = -3.0V for pulse width less than 10 ns. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. D 07/01/02 IS61C64B POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol ICC ISB1 Parameter Vcc Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) Test Conditions VCC = Max., IOUT = 0 mA, f = fMAX VCC = Max., VIN = VIH or VIL CE1 * VIH or CE2 - VIL, f = 0 VCC = Max., CE1 * VCC - 0.2V, CE2 - 0.2V, VIN * VCC - 0.2V, or VIN - 0.2V, f = 0 -10ns Min. Max. -- -- 185 30 -12 ns Min. Max. -- -- 175 30 -15ns Min. Max. -- -- 135 30 ISSI Unit mA mA (R) ISB2 CMOS Standby Current (CMOS Inputs) -- 10 -- 10 -- 10 mA Notes: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. CAPACITANCE(1,2) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 8 10 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, Vcc = 5.0V. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. D 07/01/02 IS61C64B READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time (2) ISSI -10ns Min. Max. 10 -- 2 -- -- 0 -- 2 -- -- 10 -- 10 5 -- 5 -- 5 -12ns Min. Max. 12 -- 2 -- -- 0 -- 3 -- -- 12 -- 12 6 -- 6 -- 7 -15ns Min. Max. 15 -- 2 -- -- 0 -- 3 -- -- 15 -- 15 7 -- 6 -- 8 Unit ns ns ns ns ns ns ns ns ns (R) 1 2 3 4 5 6 tRC tAA tOHA tACE tDOE tLZOE OE to Low-Z Output CE to Low-Z Output CE to High-Z Output tHZOE(2) OE to High-Z Output tLZCE1 tHZCE (2) (2) Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured 500 mV from steady-state voltage. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1a and 1b 7 8 9 AC TEST LOADS 480 5V 480 5V 10 255 OUTPUT 30 pF Including jig and scope 255 OUTPUT 5 pF Including jig and scope 11 12 Figure 1a. Figure 1b. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. D 07/01/02 IS61C64B ISSI (R) AC WAVEFORMS READ CYCLE NO. 1(1,2) tRC ADDRESS tAA tOHA tOHA DATA VALID DOUT PREVIOUS DATA VALID READ CYCLE NO. 2(1,3) tRC ADDRESS tAA tOHA OE tDOE tHZOE CE tACE tLZCE tLZOE tHZCE DATA VALID DOUT HIGH-Z Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. D 07/01/02 IS61C64B ISSI -10ns Min. Max. 10 9 9 0 0 8 8 0 -- 0 -- -- -- -- -- -- -- -- 6 -- -12ns Min. Max. 12 10 10 0 0 8 8 0 -- 0 -- -- -- -- -- -- -- -- 6 -- -15ns Min. Max. 15 12 12 0 0 10 9 0 -- 0 -- -- -- -- -- -- -- -- 7 -- Unit ns ns ns ns ns ns ns ns ns ns (R) WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) Symbol Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time WE Pulse Width Data Setup to Write End Data Hold from Write End (2) 1 2 3 4 5 6 7 8 9 10 11 12 tWC tSCE tAW tHA tSA tPWE(4) tSD tHD tHZWE WE LOW to High-Z Output tLZWE(2) WE HIGH to Low-Z Output Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. D 07/01/02 IS61C64B AC WAVEFORMS WRITE CYCLE NO. 1 (WE Controlled)(1,2) WE tWC ISSI (R) ADDRESS tSCE tHA CE tAW WE tSA tHZWE tPWE tLZWE HIGH-Z DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID WRITE CYCLE NO. 2 (CE1 CE2 Controlled)(1,2) CE1, CE1 tWC ADDRESS tSA tSCE tHA CE tAW tPWE WE tHZWE tLZWE HIGH-Z DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 2. I/O will assume the High-Z state if OE = VIH. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. D 07/01/02 IS61C64B ISSI Order Part No. IS61C64B-10J IS61C64B-10T IS61C64B-12J IS61C64B-12T IS61C64B-15J IS61C64B-15T Package 300-mil Plastic SOJ Plastic TSOP 300-mil Plastic SOJ Plastic TSOP 300-mil Plastic SOJ Plastic TSOP (R) ORDERING INFORMATION Commercial Range: 0C to +70C Speed (ns) 10 12 15 1 2 3 4 5 6 7 8 9 10 11 12 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. D 07/01/02 |
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